module Reg(clkIn,resetIn,sw_i,rs1In,rs2In,rdIn,dataIn,pcIn,writeIn,disMode,data1Out,data2Out,portOut);
  input clkIn;
  input resetIn;
  input [15:0]sw_i;
  input [4:0]rs1In;
  input [4:0]rs2In;
  input [4:0]rdIn;
  input [31:0]dataIn;
  input [31:0]pcIn;
  input writeIn;
  input disMode;
  output  [31:0]data1Out;
  output  [31:0]data2Out;
  output reg [31:0]portOut;//显示给LED

  reg [31:0] re[31:0];
  assign data1Out=re[rs1In];
  assign data2Out=re[rs2In];
  integer i;
  
  always @(sw_i) begin
    case(sw_i[1:0])
        2'b00:portOut<=re[1][31:0];
        2'b01:portOut<=pcIn;
        2'b10:portOut<=re[0][31:0];
        2'b11:portOut<={27'b000000000000000000000000000,rdIn};
        default:portOut<=32'hFFFFFFFF;    
    endcase
  end
  
  initial begin
      for (i = 0;i<32 ;i=i+1 ) begin
         re[i]<=0;
      end
  end
  always@(posedge clkIn or negedge resetIn) begin
    if(!resetIn) begin
      for (i = 0;i<32 ;i=i+1 ) begin
         re[i]<=0;
      end
    end
    else begin
        if(writeIn)begin
          re[rdIn]<=dataIn;
        end
        else re[0]<=re[0];
    end
  end

endmodule